A. Field of the invention
This invention relates generally to a fault-tolerant memory system, and more particularly to an addressing system of the block management type which excludes faulty memory blocks from those to be addressed.
B. Background Art
As the storage capacity of semiconductor memories continues to increase as a function of lower chip manufacturing costs and higher integration densities, so does the percentage of chips having too many faulty storage cells to fix using conventional on-chip fault recovery techniques such as redundancy. Accordingly, in a memory system of the "block management" type (i.e. a memory chip wherein the array of memory cells are broken up into individual sub-arrays or "blocks"), or tests are conducted when the chip is first activated to exclude those blocks containing error locations from those to be accessed.
For example, according to the invention disclosed in Published Unexamined patent application (JPUPA) no. 51-25941, a check circuit having a self-diagnosing function is provided for each memory block, so as to successively shift the input addresses, excluding the blocks in which errors have been detected. In this method, if a stationary failure (i.e. a hardware fail, as opposed to a soft error due to radiation) occurs along an address line selected by a row address and a column address, errors will be promulgated in all blocks linked t that address line.
In JPUPA No. 57-109198, a word is accessed from a plurality of memory blocks by addressing these blocks with the same row and column addresses. Normally, if two errors occur in the same word, the word will not be correctable by double error detect, single error correct (DED/SEC) error correction code (ECC) techniques. Accordingly, in the JPUPA one of the blocks in which errors occur is addressed with the row and column addresses interchanged so that another location involving no error may be addressed, whereby a plurality of errors in the same word are converted into a single error that can be corrected using ECC. This method deals with soft errors by temporarily switching the row/column address for a given memory block containing an error; always dealing with stationary errors in this way, however, is not desirable because of the prolonged processing time associated with the address interchanges for respective blocks. Moreover, only one error block is corrected in this fashion; if there are multiple error blocks, most will not be corrected and will decrease the overall storage capacity of the memory.
Further, JPUPA 63-128, 820 discloses an interleave method wherein write operations into the memory are conducted in the row direction while read operations are conducted in the column direction. Again, because a given word is read from different rows, any "burst errors" (i.e. multi-bit errors) occurring during a write are converted into random errors in reading, thereby enabling correction by ECC. However, while this method is effective for continuous data reading, it is not suitable for error correction of data which are randomly read out.
As illustrated by the art discussed above, it is generally known to provide fault tolerance by simply by passing memory blocks containing faulty cell locations. However, such systems do not adequately address burst errors encompassing a plurality of blocks, such as an address line failure wherein the circuitry activating a given row/column of cells is faulty. Simply reducing the number of usable blocks is not satisfactory where the number of blocks excluded becomes so great that the remaining memory capacity is insufficient to store the requisite amount of information, e.g., for a program.